WEPA-1: 1st Workshop on Embedded Parallel Architectures

                (dragon.kayamba.com/~enric/wepa-1.htm)

                 to be held in conjunction with the

          10th International Symposium on High Performance Computer
			Architecture

                        Madrid, Spain
                        Saturday, Feb 14th, 2004



Objectives and Scope

The workshop addresses the different issues encountered while architecting
parallel systems (multi-processor, multi-threaded, hybrid) for embedded
applications.

The workshop papers will explore the issues at the architecture level, the
support needed at the compiler and OS, the effort placed at the application
level in porting old code to the new architectures and the tools developed to
simulate the performance of the embedded systems.

The goal of this workshop is to create a forum wherein the authors can present
the issues they have encountered and the solutions they have applied in order
to solve the problems. Papers submitted to WEPA-1 must contain new research or
improvement on previous works that have not been already presented in a prior
conference.

Major topics include, but are not limited to

          * Architecture
                * Multi-processor architectures
                * Multi-threaded architectures
                * Hybrid architectures
                * Speculation and prediction techniques
                * Parallel I/O-bound architectures
                * Parallel Memory-bound architectures
                * Low-power techniques specific for parallel architectures
                * Hardware support for synchronization of threads/processors
                * Hardware support for contention and coherency
                * Debugging support
          * Compiler and OS
                * Support for thread/processor synchronization
                * Parallelization techniques
          * Applications
                * Networking (routers, security, monitoring, storage)
                * Real-time (satellite, sensoring, automotive)
                * Multimedia (DSPs, graphics)
                * etc.
          * Performance
                * Performance/Cost trade-off
                * Architectural modeling
                * Trace analysis
                * Comparison with non-parallel architectures

Workshop Co-chairs

    * Mario Nemirovsky (Kayamba, Inc.) mario@kayamba.com
    * Jean-Luc Gaudiot (UC Irvine) gaudiot@uci.edu
    * Enric Musoll (Kayamba, Inc.) enric@kayamba.com

Important Deadlines

    * Paper Submission: Oct 1st, 2003, *** Extended to Nov 23rd '03 ***
    * Author Notification: Nov 14th, 2003, *** Extended to Dec 22nd '03 ***
    * Camera-ready Papers: Dec 19th, 2003, *** Extended to Jan 12th '04 ***

Questions and Submission Procedure

    * Please submit your manuscripts and questions to enric@kayamba.com
    * Manuscripts should not exceed 8 single-column double-spaced pages, and
they should be in pdf format only.
    * The submitted file must contain an additional cover page detailing
complete author information, including contact author email.
    * Final version for the accepted papers will be allowed to have 6 pages in
usual IEEE two column conference proceedings format.